There is a continuing push to produce smaller semiconductor devices with lower power consumption and faster switching speeds. With device miniaturization, however, comes a number of new design problems. In particular, as new technologies are implemented to produce smaller device components, there is a need to retain compatibility with other components still being produced by older technologies.
For instance, consider the efforts to scale-down a metal oxide semiconductor (MOS) device. Scaling down the gate length, in addition to increasing device packing density, also facilitates the use of lower voltages and the faster operation of a field effect transistor (FET). Scaling down the gate, however, tends to increase the transistor's leakage current in the off-state. One approach to reduce the leakage current is to form a shallow source/drain extension immediately next to the gate and near the substrate's surface and the channel region. The source/drain extensions, as well understood by those skilled in the art, act as extensions of the more heavily doped source and drain region. The source/drain extensions are also widely referred to as shallow junctions or lightly doped drains (LDD).
Unfortunately, a conventionally-formed, and therefore conventionally-sized source/drain extension, used with a scaled-down gate does not necessarily cure the leakage current problem. A conventionally-sized drain extension can undesirably generate an electrical field that is sufficient to lower the gate threshold voltage and cause drain-induced barrier lowering (DIBL). The gate threshold voltage is reduced because the electric field from the drain penetrates into the channel and acts oppositely to the gate's electric field. DIBL occurs when the electric field from the drain reaches the source, thereby lowering the energy barrier to inject carriers into the channel.
Consequently, it is necessary to also scale-down the source/drain extension to reduce the strength of the electric field generated by the drain. Moreover, it is important to be able to scale down the dimensions of the source/drain extension in proportion to the degree of reduction in gate length. Source/drain extension can be scaled-down by using low dopant implant energies in combination with rapid or spike thermal annealing. The use of increasingly shorter thermal anneal times to provide smaller source/drain dimensions as devices are continuously scaled down, has been problematic, however.
As the duration of the annealing time is reduced, the dopant of the source/drain extension diffuses substantially shorter distances. This advantageously minimizes the depth of the source/drain extension in the substrate and produces extensions having a well-defined border, as exemplified by an abrupt decrease in dopant concentration in transitioning from the extension to substrate. An abrupt border is desirable as this supports the low-voltage operation of transistor devices and better defines the width of the channel region. Unfortunately, short anneal times also limit the extent to which implanted dopants of the source/drain extension diffuse under the gate.
It is desirable to form the source/drain extension such that it overlaps with the gate because this facilitates the electric field generated by the gate to cause majority carriers to accumulate in the border of the source/drain extension. The accumulation of majority carriers, in turn, helps mitigate the increased resistance associated with lower dopant concentrations in the border of the extension. High resistance in the border of the source/drain extension is undesirable because this reduces the transistor's on-state current.
Therefore there is need for an improved method to manufacture scaled-down source/drain extensions in semiconductor devices that avoid the above-mentioned limitations.